The present invention pertains to central processing unit access to memory and more particularly to an arrangement for executing program code from data memory without substantial loss of corresponding program code memory.
Present day computer central processor units (CPUs) provide control information indicating the status of whether a memory read is a program code fetch or a data fetch. This control information has been used in the past in memory decoding circuitry, so that both data memory and program code memory could each utilize the full addressing capability of the CPU. For example, a processor with a 16 bit address would be able to access 64K words of data and 64K words of program code. This implementation does not provide for certain pages of the data memory to contain program code.
Other memory decoding circuitry may alot certain pages of the data memory to contain program code, but the corresponding memory page of the program code memory then could not be used for any program code storage.
Accordingly, it is the object of the present invention to provide for the allocation of program code to data memory storage without the loss of the corresponding page of the program code for the storage of program code.